Logic-timing Simulation and the Degradation Delay Model

Przednia okładka
Imperial College Press, 2006 - 267
This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the ?Degradation Delay Model?, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s)

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Spis treści

Fundamentals of Timing Simulation
Delay Models Evolution and Trends
Degradation and Inertial Effects
CMOS Inverter Degradation Delay Model
GateLevel DDM
Logic Level Simulator Design and Implementation
DDM Simulation Results
Accurate Measurement of the Switching Activity
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