Logic-timing Simulation and the Degradation Delay ModelImperial College Press, 2006 - 267 This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the ?Degradation Delay Model?, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s) |
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... Measurements Accurate Measurement of the Switching Activity : A HALOTIS Application .239 8.7 Conclusions References . Index .244 .249 .251 .265 Chapter 1 Fundamentals of Timing Simulation Carlos Jesús Jiménez Fernández Contents xvii : 19.
... Measurements Accurate Measurement of the Switching Activity : A HALOTIS Application .239 8.7 Conclusions References . Index .244 .249 .251 .265 Chapter 1 Fundamentals of Timing Simulation Carlos Jesús Jiménez Fernández Contents xvii : 19.
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Inne wydania - Wyświetl wszystko
Logic-timing Simulation And The Degradation Delay Model Manuel Jesus Bellido Diaz,Jorge Juan Chico,Manuel Valencia Ograniczony podgląd - 2005 |
Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido,Jorge Juan Chico,Manuel Valencia Ograniczony podgląd - 2005 |
Kluczowe wyrazy i wyrażenia
accurate algorithm Auvergne behavioural model Bellido calculate capacitance cell library chapter characterization process Circuits and Systems CMOS gates CMOS inverter complex considered corresponding curves Daga degra degradation effect degradation parameters delay models delay value dependence devices digital circuits dynamic electrical simulation equations evaluate example expressions frequency function gate level glitches HALOTIS HSPICE IEEE IEEE Transactions implemented inertial delay inertial effect input collisions input pulse input transition Integrated Circuits IOCC linear logic gate logic simulation maximum metastability MOSFET netlist NMOS node normal propagation delay number of inputs number of transitions operation oscillation out7 output load overshoot PMOS post-layout precision region relative error ring oscillator sensitivity shown in Fig signals simplified model static stimuli submicron switching activity Table threshold tion transient analysis transistor transistor level Type 2 collisions types of simulation verification Verilog VLSI waveform width