Logic-timing Simulation And The Degradation Delay ModelWorld Scientific, 29 lis 2005 - 288 This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the “Degradation Delay Model”, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s) |
Z wnętrza książki
Wyniki 1 - 5 z 21
Strona ix
... verification. The latter are meant to check that each design description meets the behavioural specifications. An aspect which is often overlooked is that the tools or, rather, the precision of the results obtained with those tools, is ...
... verification. The latter are meant to check that each design description meets the behavioural specifications. An aspect which is often overlooked is that the tools or, rather, the precision of the results obtained with those tools, is ...
Strona x
... verifying the correctness of the design at the timing level but also for characterizing the performances, an aspect which may ... verification of the designs. The first chapter is devoted to the fundamental aspects of timing simulation ...
... verifying the correctness of the design at the timing level but also for characterizing the performances, an aspect which may ... verification of the designs. The first chapter is devoted to the fundamental aspects of timing simulation ...
Strona xi
... verification of the designs. On the other hand, a detailed analysis is given of the inertial effect and the so-called inertial delay, a model widely used to include this effect within the logic simulation. In this chapter it is shown ...
... verification of the designs. On the other hand, a detailed analysis is given of the inertial effect and the so-called inertial delay, a model widely used to include this effect within the logic simulation. In this chapter it is shown ...
Strona xv
... Verification of the model for the first degradation parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.6.2 Verification of the model for the second degradation parameter ...
... Verification of the model for the first degradation parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.6.2 Verification of the model for the second degradation parameter ...
Strona 1
... verification of the correctness of a layout is divided into three main areas. First of all, the verification of construction rules for layout imposed by the foundry, DRC (Design Rule Check). Secondly, it must be verified that the ...
... verification of the correctness of a layout is divided into three main areas. First of all, the verification of construction rules for layout imposed by the foundry, DRC (Design Rule Check). Secondly, it must be verified that the ...
Spis treści
1 | |
Evolution and Trends | 23 |
3 Degradation and Inertial Effects | 47 |
4 CMOS Inverter Degradation Delay Model | 75 |
5 GateLevel DDM | 127 |
6 Logic Level Simulator Design and Implementation | 181 |
7 DDM Simulation Results | 203 |
8 Accurate Measurement of the Switching Activity | 227 |
References | 251 |
Index | 265 |
Inne wydania - Wyświetl wszystko
Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido,Jorge Juan Chico,Manuel Valencia Ograniczony podgląd - 2006 |
Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido,Jorge Juan Chico,Manuel Valencia Ograniczony podgląd - 2005 |
Kluczowe wyrazy i wyrażenia
accurate algorithm Auvergne behavioural model Bellido calculate capacitance cell library chapter characterization process Circuits and Systems CMOS gates CMOS inverter complex considered corresponding coupling capacitance curves Daga degra degradation effect degradation parameters delay models delay value dependence devices digital circuits dynamic electrical simulation equations evaluate example expressions frequency function gate level glitches HALOTIS HSPICE IEEE IEEE Transactions implemented inertial delay inertial effect input collisions input pulse input transition Integrated Circuits IOCC linear logic gate logic simulation maximum metastability MOSFET netlist NMOS node normal propagation delay number of inputs number of transitions operation oscillation output load overshoot PMOS post-layout precision region relative error sensitivity short-circuit shown in Fig signals simplified model static stimuli submicron switching activity Table threshold tion transient analysis transistor level Type 2 collisions types of simulation Value Error verification Verilog VLSI waveform width