Logic-timing Simulation And The Degradation Delay ModelWorld Scientific, 29 lis 2005 - 288 This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the “Degradation Delay Model”, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s) |
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Strona viii
... digital circuits. This book constitutes a basic work of reference for any professional digital designer. It is also a reference manual for researchers developing new analysis and simulation tools for digital systems. I believe that with ...
... digital circuits. This book constitutes a basic work of reference for any professional digital designer. It is also a reference manual for researchers developing new analysis and simulation tools for digital systems. I believe that with ...
Strona ix
... digital circuits is undoubtedly one of those with the greatest sensitivity to technological variations. This, along with the fact that the aim is to achieve a maximum circuit operation speed, implies a constant scientific need for ...
... digital circuits is undoubtedly one of those with the greatest sensitivity to technological variations. This, along with the fact that the aim is to achieve a maximum circuit operation speed, implies a constant scientific need for ...
Strona x
... digital circuits. Precision in the timing analysis at gate level is of the utmost importance for several reasons. On the one hand, it is important from the point of view of the designer, who normally follows a Top-Down methodology ...
... digital circuits. Precision in the timing analysis at gate level is of the utmost importance for several reasons. On the one hand, it is important from the point of view of the designer, who normally follows a Top-Down methodology ...
Strona xii
... digital circuits. Actually, most tools for estimating the consumption of energy in digital circuits employ switching activity as a fundamental parameter. In this chapter, on the one hand, a detailed quantitative study on the ISCAS85 ...
... digital circuits. Actually, most tools for estimating the consumption of energy in digital circuits employ switching activity as a fundamental parameter. In this chapter, on the one hand, a detailed quantitative study on the ISCAS85 ...
Strona 1
... digital integrated circuits. Figure 1.1 outlines these design processes. In every design process, the tasks to test ... circuit at the transistor level. Although in some cases it is useful to start off with functional descriptions ...
... digital integrated circuits. Figure 1.1 outlines these design processes. In every design process, the tasks to test ... circuit at the transistor level. Although in some cases it is useful to start off with functional descriptions ...
Spis treści
1 | |
Evolution and Trends | 23 |
3 Degradation and Inertial Effects | 47 |
4 CMOS Inverter Degradation Delay Model | 75 |
5 GateLevel DDM | 127 |
6 Logic Level Simulator Design and Implementation | 181 |
7 DDM Simulation Results | 203 |
8 Accurate Measurement of the Switching Activity | 227 |
References | 251 |
Index | 265 |
Inne wydania - Wyświetl wszystko
Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido,Jorge Juan Chico,Manuel Valencia Ograniczony podgląd - 2006 |
Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido,Jorge Juan Chico,Manuel Valencia Ograniczony podgląd - 2005 |
Kluczowe wyrazy i wyrażenia
accurate algorithm Auvergne behavioural model Bellido calculate capacitance cell library chapter characterization process Circuits and Systems CMOS gates CMOS inverter complex considered corresponding coupling capacitance curves Daga degra degradation effect degradation parameters delay models delay value dependence devices digital circuits dynamic electrical simulation equations evaluate example expressions frequency function gate level glitches HALOTIS HSPICE IEEE IEEE Transactions implemented inertial delay inertial effect input collisions input pulse input transition Integrated Circuits IOCC linear logic gate logic simulation maximum metastability MOSFET netlist NMOS node normal propagation delay number of inputs number of transitions operation oscillation output load overshoot PMOS post-layout precision region relative error sensitivity short-circuit shown in Fig signals simplified model static stimuli submicron switching activity Table threshold tion transient analysis transistor level Type 2 collisions types of simulation Value Error verification Verilog VLSI waveform width