Logic-timing Simulation And The Degradation Delay ModelWorld Scientific, 29 lis 2005 - 288 This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the “Degradation Delay Model”, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s) |
Z wnętrza książki
Wyniki 1 - 5 z 33
Strona vii
... devices. Establishing an adequate succession of events, with respect to signal sequencing and the generation of adequate levels of voltage and current will determine the correct or incorrect functioning of the system. According to ...
... devices. Establishing an adequate succession of events, with respect to signal sequencing and the generation of adequate levels of voltage and current will determine the correct or incorrect functioning of the system. According to ...
Strona viii
... devices. The work presented here encompasses the main aspects related to the logic timing simulation of circuits and digital systems. This work arises as the product of the experience of the authors and their deep knowledge on the ...
... devices. The work presented here encompasses the main aspects related to the logic timing simulation of circuits and digital systems. This work arises as the product of the experience of the authors and their deep knowledge on the ...
Strona ix
... devices they implement lose validity with technological evolution. In order to avoid this loss of precision in the results it is necessary to carry out a constant update of the tools by analysing and improving behavioural models. The ...
... devices they implement lose validity with technological evolution. In order to avoid this loss of precision in the results it is necessary to carry out a constant update of the tools by analysing and improving behavioural models. The ...
Strona x
... devices (especially of logic gates) and the simulation tools at the logic level which allow for the timing analysis of large digital circuits. Precision in the timing analysis at gate level is of the utmost importance for several ...
... devices (especially of logic gates) and the simulation tools at the logic level which allow for the timing analysis of large digital circuits. Precision in the timing analysis at gate level is of the utmost importance for several ...
Strona xiv
... Degradation Effect . . . . . . . . . . . . . . . . . . 62 3.3.1 Maximum device operation frequency . . . . . . . . . . . . . . . . 64 3.3.2 Comparison with classical calculations and results . . . . . . 66 3.4 Inertial Effect ...
... Degradation Effect . . . . . . . . . . . . . . . . . . 62 3.3.1 Maximum device operation frequency . . . . . . . . . . . . . . . . 64 3.3.2 Comparison with classical calculations and results . . . . . . 66 3.4 Inertial Effect ...
Spis treści
1 | |
Evolution and Trends | 23 |
3 Degradation and Inertial Effects | 47 |
4 CMOS Inverter Degradation Delay Model | 75 |
5 GateLevel DDM | 127 |
6 Logic Level Simulator Design and Implementation | 181 |
7 DDM Simulation Results | 203 |
8 Accurate Measurement of the Switching Activity | 227 |
References | 251 |
Index | 265 |
Inne wydania - Wyświetl wszystko
Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido,Jorge Juan Chico,Manuel Valencia Ograniczony podgląd - 2006 |
Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido,Jorge Juan Chico,Manuel Valencia Ograniczony podgląd - 2005 |
Kluczowe wyrazy i wyrażenia
accurate algorithm Auvergne behavioural model Bellido calculate capacitance cell library chapter characterization process Circuits and Systems CMOS gates CMOS inverter complex considered corresponding coupling capacitance curves Daga degra degradation effect degradation parameters delay models delay value dependence devices digital circuits dynamic electrical simulation equations evaluate example expressions frequency function gate level glitches HALOTIS HSPICE IEEE IEEE Transactions implemented inertial delay inertial effect input collisions input pulse input transition Integrated Circuits IOCC linear logic gate logic simulation maximum metastability MOSFET netlist NMOS node normal propagation delay number of inputs number of transitions operation oscillation output load overshoot PMOS post-layout precision region relative error sensitivity short-circuit shown in Fig signals simplified model static stimuli submicron switching activity Table threshold tion transient analysis transistor level Type 2 collisions types of simulation Value Error verification Verilog VLSI waveform width