Logic-timing Simulation And The Degradation Delay ModelWorld Scientific, 29 lis 2005 - 288 This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the “Degradation Delay Model”, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s) |
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Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia. Manuel J. Bellido Jorge Juan Manuel Valencia Imperial College Press Logic-timing Simulation and the Degradation Delay Model This page intentionally. Front Cover.
Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia. Manuel J. Bellido Jorge Juan Manuel Valencia Imperial College Press Logic-timing Simulation and the Degradation Delay Model This page intentionally. Front Cover.
Strona i
Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia. Logic-timing Simulation and the Degradation Delay Model This page intentionally left blank Logic-timing Simulation and the Degradation.
Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia. Logic-timing Simulation and the Degradation Delay Model This page intentionally left blank Logic-timing Simulation and the Degradation.
Strona ii
Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia. This page intentionally left blank Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido.
Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia. This page intentionally left blank Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido.
Strona iii
Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia. Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido University of Seville, Spain & Jorge Juan | Institute for Microelectronics Manuel Valencia of Seville ...
Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia. Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido University of Seville, Spain & Jorge Juan | Institute for Microelectronics Manuel Valencia of Seville ...
Strona iv
Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia. Published by Imperial College Press 57 Shelton Street Covent Garden London WC2H 9HE Distributed by World Scientific Publishing Co. Pte. Ltd. 5 Toh Tuck Link, Singapore 596224 ...
Manuel Jesus Bellido Diaz, Jorge Juan Chico, Manuel Valencia. Published by Imperial College Press 57 Shelton Street Covent Garden London WC2H 9HE Distributed by World Scientific Publishing Co. Pte. Ltd. 5 Toh Tuck Link, Singapore 596224 ...
Spis treści
1 | |
Evolution and Trends | 23 |
3 Degradation and Inertial Effects | 47 |
4 CMOS Inverter Degradation Delay Model | 75 |
5 GateLevel DDM | 127 |
6 Logic Level Simulator Design and Implementation | 181 |
7 DDM Simulation Results | 203 |
8 Accurate Measurement of the Switching Activity | 227 |
References | 251 |
Index | 265 |
Inne wydania - Wyświetl wszystko
Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido,Jorge Juan Chico,Manuel Valencia Ograniczony podgląd - 2006 |
Logic-timing Simulation and the Degradation Delay Model Manuel J. Bellido,Jorge Juan Chico,Manuel Valencia Ograniczony podgląd - 2005 |
Kluczowe wyrazy i wyrażenia
accurate algorithm Auvergne behavioural model Bellido calculate capacitance cell library chapter characterization process Circuits and Systems CMOS gates CMOS inverter complex considered corresponding coupling capacitance curves Daga degra degradation effect degradation parameters delay models delay value dependence devices digital circuits dynamic electrical simulation equations evaluate example expressions frequency function gate level glitches HALOTIS HSPICE IEEE IEEE Transactions implemented inertial delay inertial effect input collisions input pulse input transition Integrated Circuits IOCC linear logic gate logic simulation maximum metastability MOSFET netlist NMOS node normal propagation delay number of inputs number of transitions operation oscillation output load overshoot PMOS post-layout precision region relative error sensitivity short-circuit shown in Fig signals simplified model static stimuli submicron switching activity Table threshold tion transient analysis transistor level Type 2 collisions types of simulation Value Error verification Verilog VLSI waveform width